1. Field of the Invention
The present invention relates to the field of high density interconnect structures, and more particularly, to accommodation of chip placement tolerances in such systems.
2. Background Information
A high density interconnect (HDI) structure or system which has been developed by General Electric Company offers many advantages in the compact assembly of electronic systems. For example, an electronic system such as a micro computer which incorporates 30-50 chips can be fully assembled and interconnected on a single substrate which is 2 inch long by 2 inch wide by 0.050 inch thick. Even more important, this interconnect structure can be disassembled for repair or replacement of a faulty component and then reassembled without significant risk to the good components incorporated within the system. This is particularly important where as many as 50 chips having a cost of as much as $2,000.00, each, may be incorporated in a single system on one substrate. This repairability is a substantial advance over prior connection systems in which reworking the system to replace damaged components was either impossible or involved substantial risk to the good components.
Briefly, in this high density interconnect structure, a ceramic substrate such as alumina which may be 100 mils thick and of appropriate size and strength for the overall system, is provided. This size is typically less than 2 inches square, but may be made larger or smaller. Once the position of the various chips has been specified, individual cavities or one large cavity having appropriate depth at the intended locations of differing chips, is prepared. This may be done by starting with a bare substrate having a uniform thickness and the desired size. Conventional, ultrasonic or laser milling may be used to form the cavities in which the various chips and other components will be positioned. For many systems where it is desired to place chips nearly edge-to-edge, a single large cavity is satisfactory. That large cavity may typically have a uniform depth where the semiconductor chips have a substantially uniform thickness. Where a particularly thick or a particularly thin component will be placed, the cavity bottom may be made respectively deeper or shallower to place the upper surface of the corresponding component in substantially the same plane as the upper surface of the rest of the components and the portion of the substrate which surrounds the cavity. The bottom of the cavity is then provided with a thermoplastic adhesive layer which may preferably be polyetherimide resin available under the trade name ULTEM.RTM. 6000 from the General Electric Company. The various components are then placed in their desired locations within the cavity, the entire structure is heated to about 300.degree. C. which is above the softening point of the ULTEM.RTM. polyetherimide (which is in the vicinity of 235.degree. C.) and then cooled to thermoplastically bond the individual components to the substrate. Thereafter, a polyimide film which may be Kapton.RTM. polyimide, available from E. I. du Pont de Nemours Company, which is .apprxeq.0.0005-0.003 inch (.apprxeq.12.5-75 microns) thick is pretreated to promote adhesion by reactive ion etching (RIE), the substrate and chips are then coated with ULTEM.RTM. 1000 polyetherimide resin or another thermoplastic and the Kapton film is laminated across the top of the chips, any other components and the substrate with the ULTEM.RTM. resin serving as a thermoplastic adhesive to hold the Kapton.RTM. in place. Thereafter, via holes are provided (preferably by laser drilling) in the Kapton.RTM. and ULTEM.RTM. layers in alignment with the contact pads on the electronic components to which it is desired to make contact. A metallization layer which is deposited over the Kapton.RTM. layer extends into the via holes and makes electrical contact to the contact pads disposed thereunder. This metallization layer may be patterned to form individual conductors during the process of depositing it or may be deposited as a continuous layer and then patterned using photoresist and etching. The photoresist is preferably exposed using a laser to provide an accurately aligned conductor pattern at the end of the process. Alternatively, exposure through a mask may be used.
Additional dielectric and metallization layers are provided as required in order to provide all of the desired electrical connections among the chips. Any misposition of the individual electronic components and their contact pads is compensated for by an adaptive laser lithography system which is the subject of some of the Patents and Applications which are listed hereinafter.
In this manner, the entire interconnect structure can be fabricated from start to finish (after definition of the required conductor patterns and receipt of the electronic components) in as little as .apprxeq.8-12 hours.
This high density interconnect structure provides many advantages. Included among these are the lightest weight and smallest volume packaging of such an electronic system presently available. A further, and possibly more significant advantage of this high density interconnect structure, is the short time required to design and fabricate a system using this high density interconnect structure. Prior art processes require the prepackaging of each semiconductor chip, the design of a multilayer circuit board to interconnect the various packaged chips, and so forth. Multilayer circuit boards are expensive and require substantial lead time for their fabrication. In contrast, the only thing which must be specially pre-fabricated for the HDI system is the substrate on which the individual semiconductor chips will be mounted. This substrate is a standard stock item, other than the requirement that the substrate have appropriate cavities therein for the placement of the semiconductor chips so that the interconnect surface of the various chips and the substrate will be in a single plane. In the HDI process, the required cavities may be formed in an already fired ceramic substrate by conventional or laser milling. This milling process is straightforward and fairly rapid with the result that once a desired configuration for the substrate has been established, a corresponding physical substrate can be made ready for the mounting of the semiconductor chips in as little as 1 day and typically 4 hours for small quantities as are suitable for research or prototype systems to confirm the design prior to quantity production.
The process of designing an interconnection pattern for interconnecting all of the chips and components of an electronic system on a single high density interconnect substrate normally takes somewhere between one week and five weeks. Once that interconnect structure has been defined, assembly of the system on the substrate may begin. First, the chips are mounted on the substrate and the overlay structure is built-up on top of the chips and substrate, one layer at a time. Typically, the entire process can be finished in one day and in the event of a high priority rush, could be completed in four hours. Consequently, this high density interconnect structure not only results in a substantially lighter weight and more compact package for an electronic system, but enables a prototype of the system to be fabricated and tested in a much shorter time than is required with other packaging techniques.
This high density interconnect structure, methods of fabricating it and tools for fabricating it are disclosed in U.S. Pat. No. 4,783 695, entitled "Multichip Integrated Circuit Packaging Configuration and Method" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,835,704, entitled "Adaptive Lithography System to Provide High Density Interconnect" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,714,516, entitled "Method to Produce Via Holes in Polymer Dielectrics for Multiple Electronic Circuit Chip Packaging" by C. W. Eichelberger, et al.; U.S. Pat. No. 4,780,177, entitled "Excimer Laser Patterning of a Novel Resist" by R. J. Wojnarowski et al.; U.S. patent application Ser. No. 249,927, filed Sep. 27, 1989, entitled "Method and Apparatus for Removing Components Bonded to a Substrate" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 310,149, filed Feb. 14, 1989, entitled "Laser Beam Scanning Method for Forming Via Holes in Polymer Materials" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 312,798, filed Feb. 21, 1989, entitled "High Density Interconnect Thermoplastic Die Attach Material and Solvent Die Attachment Processing" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 283,095, filed Dec. 12, 1988, entitled "Simplified Method for Repair of High Density Interconnect Circuits" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 305,314, filed Feb. 3, 1989, entitled "Fabrication Process and Integrated Circuit Test Structure" by H. S. Cole, et al.; U.S. patent application Ser. No. 250,010, filed Sep. 27, 1988, entitled "High Density Interconnect With High Volumetric Efficiency" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 329,478, filed Mar. 28, 1989, entitled "Die Attachment Method for Use in High Density Interconnected Assemblies" by R. J. Wojnarowski, et al.; U.S. patent application Ser. No. 253,020, filed Oct. 4, 1988, entitled "Laser Interconnect Process" by H. S. Cole, et al.; U.S. patent application Ser. No. 230,654, filed Aug. 5, 1988, entitled "Method and Configuration for Testing Electronic Circuits and Integrated Circuit Chips Using a Removable Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 233,965, filed Aug. 8, 1988, entitled "Direct Deposition of Metal Patterns for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,638, filed Aug. 23, 1988, entitled "Method for Photopatterning Metallization Via UV Laser Ablation of the Activator" by Y. S. Liu, et al.; U.S. patent application Ser. No. 237,685, filed Aug. 25, 1988, entitled "Direct Writing of Refractory Metal Lines for Use in Integrated Circuit Devices" by Y. S. Liu, et al.; U.S. patent application Ser. No. 240,367, filed Aug. 30, 1988, entitled " Method and Apparatus for Packaging Integrated Circuit Chips Employing a Polymer Film Overlay Layer" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 342,153, filed Apr. 24, 1989, entitled "Method of Processing Siloxane-Polyimides for Electronic Packaging Applications" by H. S. Cole, et al.; U.S. patent application Ser. No. 289,944, filed Dec. 27, 1988, entitled "Selective Electrolytic Deposition on Conductive and Non-Conductive Substrates" by Y. S. Liu, et al.; U.S. patent application Ser. No. 312,536, filed Feb. 17, 1989, entitled "Method of Bonding a Thermoset Film to a Thermoplastic Material to Form a Bondable Laminate" by R. J. Wojnarowski; U.S. patent application Ser. No. 363,646, filed Jun. 8, 1989, entitled "Integrated Circuit Packaging Configuration for Rapid Customized Design and Unique Test Capability" by C. W. Eichelberger, et al.; U.S. patent application Ser. No. 07/459,844, filed Jan. 2, 1990, entitled "Area-Selective Metallization Process" by H. S. Cole, et al.; U.S. patent application Ser. No. 361,623, filed Jun. 5, 1989, entitled, "Adaptive Lithography Accommodation of Tolerances and Chip Positioning in High Density Interconnect Structures", by T. R. Haller; U.S. patent application Ser. No. 07/457,023, filed Dec. 26, 1989, entitled "Locally Orientation Specific Routing System" by T. R. Haller, et al.; U.S. patent application Ser. No. 456,421, filed Dec. 26, 1989, entitled "Laser Ablatable Polymer Dielectrics and Methods" by H. S. Cole, et al.; U.S. patent application Ser. No. 454,546, filed Dec. 21, 1989, entitled "Hermetic High Density Interconnected Electronic System" by W. P. Kornrumpf, et al.; U.S. patent application Ser. No. 07/457,127, filed Dec. 26, 1989, entitled "Enhanced Fluorescence Polymers and Interconnect Structures Using Them" by H. S. Cole, et al.; U.S. patent application Ser. No. 454,545, filed Dec. 21, 1989, entitled "An Epoxy/Polyimide Copolymer Blend Dielectric and Layered Circuits Incorporating It" by C. W. Eichelberger, et al.; application Ser. No. 07/504,760, filed Apr. 5, 1990, entitled, "A Building Block Approach to Microwave Modules", by W. P. Kornrumpf et al.; application Ser. No. 07/504,821, filed Apr. 5, 1990, entitled, "HDI Microwave Circuit Assembly", by W. P. Kornrumpf, et al.; application Ser. No. 07/504,750 filed Apr. 5, 1990, entitled, "An Ultrasonic Array With a High Density of Electrical Connections", by L. S. Smith, et al.; application Ser. No. 07/504,803, filed Apr. 5, 1990, entitled, "Microwave Component Test Method and Apparatus", by W. P. Kornrumpf, et al.; application Ser. No. 07/504,753, filed Apr. 5, 1990, entitled, "A Compact High Density Interconnected Microwave System", by W. P. Kornrumpf; application Ser. No. 07/504,769, filed Apr. 5, 1990, entitled, "A Flexible High Density Interconnect Structure and Flexibly Interconnected System" by C. W. Eichelberger, et al.; application Ser. No. 07/504,751, filed Apr. 5, 1990, entitled, "Compact, Thermally Efficient Focal Plane Array and Testing and Repair Thereof", by W. P. Kornrumpf, et al; application Ser. No. 07/504,749, filed Apr. 5, 1990, entitled, "High Density Interconnect Structure with Top Mounted Components", by R. J. Wojnarowski, et al.; application Ser. No. 07/504,770, filed Apr. 5, 1990, entitled, "A High Density Interconnect Structure Including a Chamber", by R. J. Wojnarowski, et al.; and application Ser. No. 07/504,748, filed Apr. 5, 1990, entitled, "Microwave Component Having Tailored Operating Characteristics and Method of Tailoring" by W. P. Kornrumpf, et al. Each of these Patents and Patent Applications is incorporated herein by reference.
This high density interconnect system is now being used for the interconnection of fairly complex systems including 40 to 60 chips which are interconnected by 1500 to 3000 nodes with the result that a computerized router typically requires relatively long runs (of from 10 to 24 hours) to successfully route all the interconnections and, in some cases, is unable to route some of the interconnections when using only two signal layers.
In a high density interconnect system of the general type discussed above, the pattern of each metallization layer and the via holes in each dielectric layer must either be individually tailored to the exact positions of the various integrated circuit chips (as placed) or an adaptive lithography system must adjust an ideal metallization and via hole pattern in accordance with the actual position of the various integrated circuit chips. In the above-identified related U.S. Pat. No. 4,835,704, this problem is solved by adaptation of an ideal metallization pattern in accordance with the actual location of each of the integrated circuits chips and its contact pads by modifying the metallization pattern to properly connect to those contact pads in their actual positions. That adaptation is enabled by providing a "picture frame" around the allowed location of each integrated circuit chip in which adaptation of the metal layer takes place. In order to facilitate that adaptation, one of the design rules for the ideal metallization is that each metal path which crosses a picture frame must do so perpendicular to those sides of that picture frame which it crosses. The ideal metallization pattern over each chip is maintained with respect to the chip and thus, must be shifted and/or rotated with respect to the portion of the metallization pattern outside the picture frame in accordance with any shift and/or rotation of the chip with respect to its ideal location. The ideal metallization pattern outside the outer edges of the picture frames is maintained with respect to the substrate, i.e. unchanged during the adaptation process. Adaptation to the actual location of each chip is accomplished by modifying the metallization pattern within the picture frame area for that chip to properly connect from the ideal metallization pattern at the outside edge of that picture frame to the shifted/rotated ideal metallization pattern over that chip. This results in the angling of conductors within its picture frame when the chip is displaced perpendicular to, or rotated with respect to its ideal position relative to a side of the picture frame.
The above-identified application Ser. No. 361,623 entitled "Adaptive Lithography Accommodation of Tolerances in Chip Positioning in High Density Interconnect Structures" provides accommodation for chip positioning placement tolerances by including contact islands in the signal layers of the high density interconnect structure where via connections are to be made to contact pads, with the contact islands being large enough to ensure that as long as the chips are placed within normal tolerances, each contact island in the signal layer will overlap its associated contact pad on the chip by a sufficient amount to enable a via hole to be positioned where it overlaps the contact pad and is, in turn, overlapped by contact island in the signal layer. While this is effective, it has the disadvantage where a high density of interconnections is required of including in the signal layer relatively large contact islands (typically 4 mils square (.about.100 microns square) for 4 mil contact pads on 8 mil centers) whereas the conductor runs themselves are only 1.5 mils wide (.about.40 microns wide) and in the U.S. Pat. No. 4,835,704 technique, would require only a 2 mil square cover pad centered over the via. This technique accommodates a maximum tolerance on chip placement of .+-.2 mils when a 2 mil by 2 mil overlap is required at a via. For larger placement tolerances, the contact islands can be made 6 mils square, but then signal conductors cannot run between adjacent contact islands.
As a consequence of the presence of these large contact islands, conductor runs in the signal layers must be spaced further apart than would otherwise be necessary in order to maintain design rule clearances between contact islands and adjacent signal runs. To ensure proper coverage of via holes between properly aligned conductors, it is presently preferred to include a cover pad in a signal conductor at the location of such a via hole, that cover pad is only 2 mils square (.about.50 microns square) and thus has a much smaller effect on wiring density than the contact islands of application Ser. No. 361,623 have. Application Ser. No. 361,623 discusses in its discussion of its FIG. 10, the placement of its contact islands in a different conductor layer when the contact islands must be made large enough that they prevent the placement of another conductor between adjacent contact islands.
Application Ser. No. 07/457,023 entitled "Locally Orientation Specific Routing System" reduces the restrictions on the placement of signal conductors by the routing program by allowing conductors to run both vertically and horizontally in each layer of the high density interconnect structure except in restricted areas in the vicinity of the edges of chips. In the vicinity of the edges of chips, conductors in every layer are restricted to running perpendicular to that edge of the chip in order to allow for the changes in orientation of the conductors in that portion of the routing plane which are produced in accordance with U.S. Pat. No. 4,835,704 when a chip is displaced from its ideal location.
As this high density interconnect structure system has matured, increased attention has been directed to its use in relatively large quantity production of complex systems which require several signal layers for their interconnection. Where adaptation is required in every conductor layer of a high density interconnect structure, the conductor pattern of each layer is individually written by a laser. Consequently, in production environment, throughput can be laser limited with a consequent requirement for multiple lasers.
Consequently, there is a need for an improved technique for accommodating chip placement tolerances in a high density interconnect structure.